Resumo

TOLEDO DE LA GARZA, Karel; TORRES GOMEZ, Jorge  e  RODRIGUEZ SUAREZ, Juan R.. Envelope Detector Development for BFSK signals in VHDL. EAC [online]. 2013, vol.34, n.2, pp. 63-75. ISSN 1815-5928.

This paper concerns demodulator-based Envelope Detector for recovery information in BFSK signal applied upon applications where time symbol synchronization is unknown. Its structure is characterized by 4 filters which are considered in the present article by FIR, this are unconditionally stables and are always implemented by the same generic difference equation. In the present work this demodulator is configured in VHDL language with a variable number of coefficients not specified in advance and conformed it in an IP module we obtain a reconfigurable circuit. In order to validate the system an FPGA from Xilinxwith PC serial communication is implemented. FPGA design comprises a Microblaze microcontroller with an Envelope Detector IP module and aRS-232 IP module for communication.A Matlab user application on PC to manage demodulation process is also implemented, it takes into account not also to send and receive the modulated and demodulated signal, but to send the coefficients values employed by the FIR filters in a specific application. The final solution allows demodulation of BFSK signals through the interconnection of Matlab with Microblaze and this with the IP module in Xilinx environment.Details of VHDL design and its results are discussed taking into account the effect of coefficient quantization, temporal analysis and FPGA occupancy.

Palavras-chave : BFSK; envelope detector; FPGA.

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