Resumen

GONZALEZ GARCIA, Alejandro  y  DIAZ HERNANDEZ, Reinier. Diseño de un receptor DVB-S en VHDL utilizando las herramientas del entorno MATLAB/Simulink. EAC [online]. 2020, vol.41, n.3, pp.66-78.  Epub 01-Dic-2020. ISSN 1815-5928.

Satellite broadcasting systems are an economical alternative for the deployment of television and other services in sparsely populated and difficult to access areas. This paper presents the modeling and hardware implementation of a DVB-S receiver according to the specifications contained in the EN 300 421 standard. The receiver is modeled and validated within the Simulink environment. From the validated model, an equivalent VHDL code is generated using the HDL Coder and HDL Verifier tools. Both Simulink synthesizable HDL modules and Xilinx Core Generator IP modules are used in the design for implementation and validation in a hardware environment, using the FPGA in the Loop tool. A comparison is made between implementation with native HDL blocks from the Simulink environment and the use of modules from the Xilinx platform.

Palabras clave : DVB-S; HDL Coder; FPGA-in-the-Loop; Simulink; Xilinx Core Generator.

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