<?xml version="1.0" encoding="ISO-8859-1"?><article xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<front>
<journal-meta>
<journal-id>1815-5928</journal-id>
<journal-title><![CDATA[Ingeniería Electrónica, Automática y Comunicaciones]]></journal-title>
<abbrev-journal-title><![CDATA[EAC]]></abbrev-journal-title>
<issn>1815-5928</issn>
<publisher>
<publisher-name><![CDATA[Universidad Tecnológica de La Habana José Antonio Echeverría, Cujae]]></publisher-name>
</publisher>
</journal-meta>
<article-meta>
<article-id>S1815-59282020000300066</article-id>
<title-group>
<article-title xml:lang="es"><![CDATA[Diseño de un receptor DVB-S en VHDL utilizando las herramientas del entorno MATLAB/Simulink]]></article-title>
</title-group>
<contrib-group>
<contrib contrib-type="author">
<name>
<surname><![CDATA[González García]]></surname>
<given-names><![CDATA[Alejandro]]></given-names>
</name>
<xref ref-type="aff" rid="Aff"/>
</contrib>
<contrib contrib-type="author">
<name>
<surname><![CDATA[Diaz Hernández]]></surname>
<given-names><![CDATA[Reinier]]></given-names>
</name>
<xref ref-type="aff" rid="Aff"/>
</contrib>
</contrib-group>
<aff id="Af1">
<institution><![CDATA[,Instituto de Investigación y Desarrollo de Telecomunicaciones  ]]></institution>
<addr-line><![CDATA[ La Habana]]></addr-line>
<country>Cuba</country>
</aff>
<pub-date pub-type="pub">
<day>00</day>
<month>12</month>
<year>2020</year>
</pub-date>
<pub-date pub-type="epub">
<day>00</day>
<month>12</month>
<year>2020</year>
</pub-date>
<volume>41</volume>
<numero>3</numero>
<fpage>66</fpage>
<lpage>78</lpage>
<copyright-statement/>
<copyright-year/>
<self-uri xlink:href="http://scielo.sld.cu/scielo.php?script=sci_arttext&amp;pid=S1815-59282020000300066&amp;lng=en&amp;nrm=iso"></self-uri><self-uri xlink:href="http://scielo.sld.cu/scielo.php?script=sci_abstract&amp;pid=S1815-59282020000300066&amp;lng=en&amp;nrm=iso"></self-uri><self-uri xlink:href="http://scielo.sld.cu/scielo.php?script=sci_pdf&amp;pid=S1815-59282020000300066&amp;lng=en&amp;nrm=iso"></self-uri><abstract abstract-type="short" xml:lang="es"><p><![CDATA[RESUMEN Los sistemas de radiodifusión satelital son una alternativa económica para el despliegue de la televisión y otros servicios en áreas poco pobladas y de difícil acceso. En el presente trabajo se presenta la modelación e implementación hardware de un receptor DVB-S según las especificaciones contenidas en el estándar EN 300 421. El receptor es modelado y validado dentro del entorno Simulink. A partir del modelo validado se genera un código VHDL equivalente utilizando las herramientas HDL Coder y HDL Verifier. En su diseño se utilizan tanto módulos HDL sintetizables de Simulink, como módulos IP del Xilinx Core Generator para su implementación y validación sobre un entorno hardware, se utiliza la herramienta FPGA in the Loop Se realiza una comparación entre la implementación con bloques HDL nativos del entorno Simulink y la utilización de módulos de la plataforma Xilinx.]]></p></abstract>
<abstract abstract-type="short" xml:lang="en"><p><![CDATA[ABSTRACT Satellite broadcasting systems are an economical alternative for the deployment of television and other services in sparsely populated and difficult to access areas. This paper presents the modeling and hardware implementation of a DVB-S receiver according to the specifications contained in the EN 300 421 standard. The receiver is modeled and validated within the Simulink environment. From the validated model, an equivalent VHDL code is generated using the HDL Coder and HDL Verifier tools. Both Simulink synthesizable HDL modules and Xilinx Core Generator IP modules are used in the design for implementation and validation in a hardware environment, using the FPGA in the Loop tool. A comparison is made between implementation with native HDL blocks from the Simulink environment and the use of modules from the Xilinx platform.]]></p></abstract>
<kwd-group>
<kwd lng="es"><![CDATA[DVB-S]]></kwd>
<kwd lng="es"><![CDATA[HDL Coder]]></kwd>
<kwd lng="es"><![CDATA[FPGA-in-the-Loop]]></kwd>
<kwd lng="es"><![CDATA[Simulink]]></kwd>
<kwd lng="es"><![CDATA[Xilinx Core Generator]]></kwd>
<kwd lng="en"><![CDATA[DVB-S]]></kwd>
<kwd lng="en"><![CDATA[HDL Coder]]></kwd>
<kwd lng="en"><![CDATA[FPGA-in-the-Loop]]></kwd>
<kwd lng="en"><![CDATA[Simulink]]></kwd>
<kwd lng="en"><![CDATA[Xilinx Core Generator]]></kwd>
</kwd-group>
</article-meta>
</front><back>
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