<?xml version="1.0" encoding="ISO-8859-1"?><article xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<front>
<journal-meta>
<journal-id>1815-5928</journal-id>
<journal-title><![CDATA[Ingeniería Electrónica, Automática y Comunicaciones]]></journal-title>
<abbrev-journal-title><![CDATA[EAC]]></abbrev-journal-title>
<issn>1815-5928</issn>
<publisher>
<publisher-name><![CDATA[Universidad Tecnológica de La Habana José Antonio Echeverría, Cujae]]></publisher-name>
</publisher>
</journal-meta>
<article-meta>
<article-id>S1815-59282022000100001</article-id>
<title-group>
<article-title xml:lang="es"><![CDATA[Formador digital de múltiples diagramas simultáneos basado en FPGA y el transceptor AD9361]]></article-title>
<article-title xml:lang="en"><![CDATA[Digital beamforming of multiple simultaneous pattern based on FPGA and the Transceiver AD9361]]></article-title>
</title-group>
<contrib-group>
<contrib contrib-type="author">
<name>
<surname><![CDATA[Ramírez Zaldívar]]></surname>
<given-names><![CDATA[Alexander R.]]></given-names>
</name>
<xref ref-type="aff" rid="Aff"/>
</contrib>
<contrib contrib-type="author">
<name>
<surname><![CDATA[Rojas Ramírez]]></surname>
<given-names><![CDATA[Noslen]]></given-names>
</name>
<xref ref-type="aff" rid="Aff"/>
</contrib>
<contrib contrib-type="author">
<name>
<surname><![CDATA[Hernández Violat]]></surname>
<given-names><![CDATA[Abel]]></given-names>
</name>
<xref ref-type="aff" rid="Aff"/>
</contrib>
<contrib contrib-type="author">
<name>
<surname><![CDATA[Ibarra Guerra]]></surname>
<given-names><![CDATA[Yunior]]></given-names>
</name>
<xref ref-type="aff" rid="Aff"/>
</contrib>
<contrib contrib-type="author">
<name>
<surname><![CDATA[Peña Sierra]]></surname>
<given-names><![CDATA[Addiel]]></given-names>
</name>
<xref ref-type="aff" rid="Aff"/>
</contrib>
</contrib-group>
<aff id="Af1">
<institution><![CDATA[,Centro de Investigación y Desarrollo de Electrónica y Mecánica &#8220;CID MECATRONICS&#8221;  ]]></institution>
<addr-line><![CDATA[La Habana ]]></addr-line>
<country>Cuba</country>
</aff>
<pub-date pub-type="pub">
<day>00</day>
<month>04</month>
<year>2022</year>
</pub-date>
<pub-date pub-type="epub">
<day>00</day>
<month>04</month>
<year>2022</year>
</pub-date>
<volume>43</volume>
<numero>1</numero>
<fpage>1</fpage>
<lpage>15</lpage>
<copyright-statement/>
<copyright-year/>
<self-uri xlink:href="http://scielo.sld.cu/scielo.php?script=sci_arttext&amp;pid=S1815-59282022000100001&amp;lng=en&amp;nrm=iso"></self-uri><self-uri xlink:href="http://scielo.sld.cu/scielo.php?script=sci_abstract&amp;pid=S1815-59282022000100001&amp;lng=en&amp;nrm=iso"></self-uri><self-uri xlink:href="http://scielo.sld.cu/scielo.php?script=sci_pdf&amp;pid=S1815-59282022000100001&amp;lng=en&amp;nrm=iso"></self-uri><abstract abstract-type="short" xml:lang="es"><p><![CDATA[RESUMEN El presente trabajo muestra el proceso de obtención de un formador digital de múltiples diagramas direccionales simultáneos para la recepción de señales utilizando la tarjeta de evaluación ARRadio. La tarjeta se basa en el transceptor integrado AD9361 y garantiza la recepción, digitalización y envío hacia un FPGA (del inglés Field Programmable Gate Array) de las ondas de radio recibidas por cada canal de radio frecuencia. El FPGA se encuentra ubicado en la tarjeta de desarrollo TR4. La comunicación entre el FPGA y cada ARRadio se realiza a través de un conector de alta velocidad. En el dispositivo programable se efectúan la configuración y control del AD9361, el proceso de calibración multicanal basado en Transformada de Fourier (como método de medición del retardo entre canales) y la formación de múltiples diagramas direccionales simultáneos de manera digital. Simulink es usado como herramienta de diseño para el desarrollo del sistema digital. Finalmente se realiza la implementación y verificación experimental del sistema formador de múltiples diagramas direccionales simultáneos.]]></p></abstract>
<abstract abstract-type="short" xml:lang="en"><p><![CDATA[ABSTRACT This paper shows the obtaining process of a digital beamformer of multiple simultaneous directional patterns for signals reception using the ARRadio evaluation board. The board is based on the integrated transceiver AD9361 and guarantees the reception, digitization and seending to an FPGA (Field Programmable Gate Array) of the received radio waves by each radiofrequency channel. The FPGA is located on the TR4 Development Board. Communication between FPGA and ARRadio is realized through a high speed connector. On the programmable device are performed AD9361&#8217;s configuration and control, multichannel calibration process based on Fourier Transform (as method of measuring the delay between channels) and beamforming of multiple simultaneous directional patterns digitally. Simulink is used as design tool for digital system develop. Finally is realized the implementation and experimental verification of multiple digital beamforming system.]]></p></abstract>
<kwd-group>
<kwd lng="es"><![CDATA[Formación digital de diagramas]]></kwd>
<kwd lng="es"><![CDATA[ARRadio]]></kwd>
<kwd lng="es"><![CDATA[AD9361]]></kwd>
<kwd lng="es"><![CDATA[FPGA]]></kwd>
<kwd lng="es"><![CDATA[Simulink]]></kwd>
<kwd lng="en"><![CDATA[Digital Beamforming]]></kwd>
<kwd lng="en"><![CDATA[ARRadio]]></kwd>
<kwd lng="en"><![CDATA[AD9361]]></kwd>
<kwd lng="en"><![CDATA[FPGA]]></kwd>
<kwd lng="en"><![CDATA[Simulink]]></kwd>
</kwd-group>
</article-meta>
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